In-Network-Processing: State-of-the-Art and Outlook
Date: Friday, 19 March 2021
Host: Prof. Dr.-Ing Andreas Koch and Prof. Dr. Carsten Binnig
With the ever-growing data volumes and transmission rates, In-Network Processing (INP) is becoming an attractive alternative to conventional architectures, where networking (e.g., switches, NICs) and compute operations (servers) are strictly separated. With In-Network Processing, data can be operated on while being in-transit between nodes. The efficient implementation of INP is dependent on novel high-performance computing elements specialized for these applications. Examples for this include the use of many-core CPUs in SmartNICs, but also specialized FPGA-based hardware accelerators that can keep up with the bandwidth and latency demands even for the network traffic in a many-port SmartSwitch. The workshop will examine different use-cases and architectures for a number of In-Network-Processing approaches and discuss the underlying technologies and their characteristics.
| 01:15 pm | Warming up, come together |
| 01:30 pm |
Andreas Koch and Carsten Binnig (TU Darmstadt, Germany) Welcome and Introduction |
| 01:50 pm |
Wayne Luk
(Imperial College London, United Kingdom) ''Codifying optimisation strategies by meta-programming'' |
| 02:40 pm | Coffee break |
| 03:00 pm |
Mosharaf Chowdhury
(University of Michigan, USA) ''Leveraging In‐Network Processing for Practical Memory Disaggregation'' |
| 03:50 pm |
Gustavo Alonso
(ETH Zürich, Switzerland) ''Smart-NICs on FPGAS and their applications'' |
| 04:40 pm | Coffee break |
| 05:00 pm |
Michaela Blott
(Xilinx Inc., San Jose, USA) ''Specialization in Hardware Architectures for Deep Learning'' |
| 05:50 pm |
Huynh Tu Dang
(Western Digital Corporation, San Jose, USA) ''Building Cache-coherent Scaleout Systems with Omnixtend'' |
| 06:40 pm |
Andreas Koch and Carsten Binnig Closing Remarks |
| 07:00 pm | End of the workshop |
